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nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 1 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. based on ddr 3 - 1066 /1333 256 mx 8 ( 2 gb/ 4 gb) / 512 mx4 (4gb / 8gb) sdram b - die based on ddr 3 - 1066 1 g x4 (ddp) (16gb) sdram b - die features ?performance: speed sort pc 3 - 8500 pc 3 - 1 060 0 unit - be - cg dimm cas latency 7 9 fck C C C ? 2 40 - pin registered dual in - line memory module ( r dimm) ? 2gb /4gb : 256mx 72 /512mx72 ddr 3 registered dimm based on 256 mx 8 ddr 3 sdram b - die devices ? 4gb /8gb : 512 mx 72 /1024mx72 ddr3 registered dimm based on 512 mx4 ddr 3 sdram b - die devices ? 16 gb: 2 g x 72 ddr3 registered dimm based on 1024 mx4 ( ddp ) ddr 3 sdram b - die devices ? intended for 533 mhz /667mhz applications ? inputs and outputs are sstl - 1 5 compatible ? v dd = v ddq = 1. 5v 0.0 75 v (for ddr3) ? v dd = v ddq = 1.35v - 0.0675/ + 0.1v (for ddr3l) ? sdrams have 8 internal banks for concurrent operation ? differential clock inputs ? data is read or written on both clock edges ? dram dll aligns dq and dqs transitions with clock t ransitions. ? address and control signals are fully synchronous to positive clock edge ? nominal and dynamic on - die termination support ? programmable operation: - dimm ??? latency: 6 ,7,8 ,9 - burst type: sequential or interleave - burst length: bc 4, bl 8 - operation: burst read and write ? two different termination values (rtt_nom & rtt_wr) ? 1 5 /1 0 / 1 (row/column/rank) addressing for 2 gb ? 1 5 /1 1 / 1 (row/column/rank) addressing for 4 gb (512mx4 device) ? 1 5 /1 0 / 2 (row/column/rank) addressing for 4 gb ( 256 mx8 device) ? 1 5 /1 1 / 2 (row/column/rank) addressing for 8 gb ? 1 5 /1 1 / 4 (row/column/rank) addressing for 16 gb ? extended operating temperature rage ? auto self - refresh option ? serial presence detect ? gold contacts ? sdrams are in 78 - ball bga package ? rohs complian ce and halogen free description nt2gc72b89b0nj , nt2gc72b89b2nj , nt2gc72c89b0nj , nt2gc72c89b2nj , nt4gc72b4pb0nl , n t4gc72c4pb0nl , nt4gc72c4pb2nl , nt4gc72b8pb0nl , nt4gc72c8pb0nl , nt4gc72c8pb2nl , nt8gc72b4nb1nj , nt8gc72b4nb3nj , nt8gc72c4nb1nj , nt8gc72c4nb3nj , nt16tc72b4nb1nl , nt16tc72c4nb1nl and nt16tc72c4nb3nl are 240 - pin double data rate 3 (ddr 3 ) synchronous dram registered dual in - line memory module, organized as one rank of 256 mx 72 ( 2 g b) , one rank or two ranks of 512 mx 72 ( 4 gb) , two ranks of 1g x 72 ( 8 gb) and four ranks of 2 g x 72 ( 16 gb) high - speed memory array. modules use nine 256 mx 8 ( 2 g b ) 78 - ball bga packaged devices , eighteen 256 mx8 ( 4 gb) 78 - ball bga packaged devices , thirty - six 512 mx 4 ( 8 gb) 78 - ball bga packaged devices and thirty - six 1g x 4 ( ddp ) ( 16 gb) 78 - ball b ga packaged devices . these dimms are manufactured using raw cards developed for broad industry use as reference designs. the use of these common design files minimizes electrical variation between suppliers. all nanya ddr 3 sdram dimms provide a high - performance, flexible 8 - byte interface in a 5.25 long space - saving footprint. the dimm is intended for use in applications operating of 533 mhz /667mhz clock speeds and achieves high - speed data transfer rates of 1066 mbps /1333mbps . prior to any access operation, the device ??? latency and burst /length/operation type must be programmed into the dimm by address inputs a0 - a1 4 and i/o inputs ba0~ ba 2 using the mode register set cycle. the dimm uses serial presence - detect implemented via a serial eeprom using a standard iic protocol . the first 128 bytes of s pd data are programmed and locked during module assembly. the remaining 128 bytes are available for use by the customer.
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 2 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ordering information part number speed organization power leads note nt2gc72b89b0nj - cg ddr3 - 1333 pc3 - 10600 667mhz (1.5ns @ cl = 9) 256mx72 1.5v gold nt2gc72b89b2nj - cg ddr3 - 1333 pc3 - 10600 667mhz (1.5ns @ cl = 9) nt4gc72b4pb0nl - cg ddr3 - 1333 pc3 - 10600 667mhz (1.5ns @ cl = 9) 512mx72 nt4gc72b8pb0nl - cg ddr3 - 1333 pc3 - 10600 667mhz (1.5ns @ cl = 9) nt8gc72b4nb 1 nj - cg ddr3 - 1333 pc3 - 10600 667mhz (1.5ns @ cl = 9) 1gx72 nt8gc72b4nb 3 nj - cg ddr3 - 1333 pc3 - 10600 667mhz (1.5ns @ cl = 9) nt16tc72b4nb1nl - be ddr3 - 1066 pc3 - 8500 533mhz (1.875ns @ cl = 7) 2gx72 nt2gc72c89b0nj - cg ddr3 l - 1333 pc3 l - 10600 667mhz (1.5ns @ cl = 9) 256mx72 1.35v nt2gc72c89b 2 nj - cg ddr3 l - 1333 pc3 l - 10600 667mhz (1.5ns @ cl = 9) nt4gc72c4pb 0 nl - cg ddr3 l - 1333 pc3 l - 10600 667mhz (1.5ns @ cl = 9) 512mx72 nt4gc72c4pb 2 nl - cg ddr3 l - 1333 pc3 l - 10600 667mhz (1.5ns @ cl = 9) nt4gc72c8pb 0 nl - cg ddr3 l - 1333 pc3 l - 10600 667mhz (1.5ns @ cl = 9) nt4gc72c8pb 2 nl - cg ddr3 l - 1333 pc3 l - 10600 667mhz (1.5ns @ cl = 9) nt8gc72c4nb 1 nj - cg ddr3 l - 1333 pc3 l - 10600 667mhz (1.5ns @ cl = 9) 1gx72 nt8gc72c4nb 3 nj - cg ddr3 l - 1333 pc3 l - 10600 667mhz (1.5ns @ cl = 9) nt16tc72c4nb 1 nl - be ddr3 l - 1066 pc3 l - 8500 533mhz (1.875ns @ cl = 7) 2gx72 nt16tc72c4nb 3 nl - be ddr3 l - 1066 pc3 l - 8500 533mhz (1.875ns @ cl = 7) pin description pin name description pin name description ck0 , ck1 clock inputs, positive line odt0, odt1 active termination control lines ??? , ??? clock inputs, negative line dq0 - dq63 data input/output cke0 , cke1 clock enable dqs0 - dqs 17 d ata strobes ??? row address strobe ??? ? - ??? ?? data strobes complement ??? column address strobe tdqs9 - tdqs17 termination data strobes ?? write enable ????? - ?????? ? termination data strobes ?? - ?? ? chip selects dm0 - dm8 data masks a0 - a9, a1 1, a13 address inputs cb0 - cb7 ecc check bits a10/ap address input/auto - p recharge ????? ? temperature event pin a1 2 / ?? address input/ burst chop ????? ? reset pin ba0 - ba2 sdram bank address inputs v ref dq , v ref ca input/output reference scl serial presence detect clock input v ddspd spd and temp sensor power sda serial presence detect data input/output sa0, sa1 , sa2 serial presence detect address inputs par_in parity bit for the address and control bus vtt termination voltage ??????? ? parity error found on the address and control bus v ss ground nc no connect v dd core and i/o power
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 3 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ddr3 sdram pin assignment pin front pin back pin front pin back pin front pin back pin front pin back 1 v refdq 121 v ss 31 dq25 151 v ss 61 a2 181 a 1 91 dq41 211 v ss 2 v ss 122 dq4 32 v ss 152 dm3/dqs12 /tdqs12 62 v dd 182 v dd 92 v ss 212 dm 5 /dqs1 4 /tdqs1 4 3 dq0 123 dq5 33 ???? 1 5 3 nc/ ????? ? / ?????? 63 nc 183 v dd 93 ???? 213 nc/ ???? ? ? / ????? ? 4 dq1 124 v ss 34 dq s3 154 v ss 64 nc ? 184 ck0 94 dqs5 214 v ss 5 v ss 125 dm0 /dqs9/ tdqs9 35 v ss 155 dq30 65 v dd 185 ??? ? 95 v ss 215 dq46 6 ???? ? 126 nc / ???? ? / ????? 36 dq26 156 dq31 66 v dd 186 v dd 96 dq42 216 dq47 7 dqs0 127 v ss 37 dq27 157 v ss 67 v refca 187 ????? ? 97 dq43 217 v ss 8 v ss 128 dq6 38 v ss 158 cb4 68 par_in /nc 188 a0 98 v ss 218 dq52 9 dq2 129 dq7 39 cb0 159 cb5 69 v dd 189 v dd 99 dq48 219 dq53 10 dq3 130 v ss 40 cb1 160 v ss 70 a10/ap 190 ba1 100 dq 49 220 v ss 11 v ss 131 dq12 41 v ss 161 dm 8 /dqs1 7 /tdqs1 7 71 ba0 191 v dd 10 1 v ss 221 dm 6 /dqs1 5 /tdqs1 5 12 dq8 132 dq13 42 ???? ? 162 nc/ ???? ? ? / ????? ? 72 v dd 192 ??? ? 102 ???? 222 nc/ ???? ? ? / ????? ? 13 dq9 133 v ss 43 dqs8 163 v ss 73 ?? ? 193 ?? ? 103 dqs6 223 v ss 14 v ss 134 dm1/dqs10 /tdqs10 44 v ss 164 cb6 74 ??? ? 194 v dd 104 v ss 224 dq54 15 ???? 135 nc/ ????? ? / ?????? 45 cb2 165 cb7 75 v dd 195 odt0 105 dq50 225 dq55 16 dqs1 136 v ss 46 cb3 166 v ss 76 ?? /nc 196 a13 106 dq51 226 v ss 17 v ss 137 dq1 4 47 v ss 167 nc 77 odt1 /nc 197 v dd 107 v ss 227 dq60 18 dq 10 138 dq15 48 v tt / nc 168 ????? ? 78 v dd 198 ?? / nc 108 dq56 228 dq61 19 dq 11 139 v ss 49 v tt / nc 169 cke1/nc 79 ?? / nc 199 v ss 109 dq57 229 v ss 20 v ss 140 dq20 50 cke0 170 v dd 80 v ss 200 dq36 110 v ss 230 dm 7 /dqs1 6 /tdqs1 6 21 dq 16 141 dq21 51 v dd 171 nc 81 dq32 201 dq37 111 ???? 231 nc/ ???? ? ? / ????? ? 22 dq 17 142 v ss 52 ba2 172 nc 82 dq33 202 v ss 112 dqs7 232 v ss 23 v ss 143 dm 2 /dqs1 1 /tdqs1 1 53 ??????? /nc 173 v dd 83 v ss 203 dm4/dqs13 /tdqs13 113 v ss 233 dq62 24 ???? 144 nc/ ???? ? ? / ????? ? 5 4 v dd 174 a1 2 / ?? 84 ???? 204 nc/ ????? ? / ?????? 114 dq58 234 dq63 25 dqs2 145 v ss 55 a11 175 a9 85 dqs4 205 v ss 115 dq59 235 v ss 26 v ss 146 dq22 56 a7 176 v dd 86 v ss 206 dq38 116 v ss 236 v ddspd 27 dq 18 147 dq23 57 v dd 177 a8 87 dq34 207 dq39 117 sa0 237 sa1 28 dq 19 148 v ss 58 a5 178 a6 88 dq35 208 v ss 118 scl 238 sda 29 v ss 149 dq28 59 a4 179 v dd 89 v ss 209 dq44 119 sa2 239 v ss 30 dq 24 150 dq29 60 v dd 180 a3 90 dq40 210 dq45 120 v tt 240 v tt note: 1. cke 1, ?? and odt1 are for 2gb /4gb /8gb only. 2. ? ? and ? ? are for 8gb only. 3. tdqs9 - tdqs17 and ????? - ?????? are for 1gb/2gb only.
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 4 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0 , ck1 ??? , ??? input cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and falling edge of ?? . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized t o the input clock. however, ck1 and ??? are terminated but not used on rdimms. cke0 , cke1 input active high activates the ddr3 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. ?? C ?? ? input active low enable the command decoders for the associated rank of sdram when low and disables decoders when high. when decoders are disabled, new commands are ignored and previous operations continue. other combinations of these input signals perform unique functions, including disabling all outputs (except cke and odt) of the register(s) on the dimm or accessing internal control words in the register device(s). for modules with two registers, ?? and ?? operate similarly to ?? and ?? for the second set of register outputs or register control words. ??? , ??? , ?? input active low when sampled at the positive rising edge of ck and falling edge of ?? , signals ??? , ??? , ?? define the operation to be executed by the sdram. odt0, odt1 input active high asserts on - die termination for dq, dm, dqs, and ??? signals if enabled via the ddr3 sdram mode register. dm0 C dm 8 input active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dq s 0 C dq s17 ???? C ??? ?? i/o cross point the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is cen tered in the data window. in read mode, the data strobe is sourced by the ddr3 sdram and is sent at the leading edge of the data window. ??? signals are complements, and timing is relative to the cross point of respective dqs and ??? . if the module is to b e operated in single ended strobe mode, all ??? signals must be tied on the system board to v ss and ddr3 sdram mode registers programmed appropriately. t dq s9 C t dq s17 ????? C ?????? out put tdqs / ???? is applicable for x8 drams only. when enabled via m ode r egister a11=1 in mr1, dram will enable the same termination resistance function on tdqs/ ???? that is applied to dqs/ ??? . when disabled via mode register a11=0 in mr1, dm/tdqs will provide the data mask function ???? is not used. x 4/x16 drams must disable the tdqs function via mode register a11=0 in mr1. ba0, ba1, ba2 input - selects which ddr3 sdram internal bank of four or eight is activated. a0 C a9 a10/ap a1 1 a12 / ?? ? a13 input - during a bank activate command cycle, defines the row address when sampled at the cross point of the rising edge of ck and falling edge of ?? . during a read or write command cycle, defines the column address when sampled at the cross point of the rising ed ge of ck and falling edge of ?? . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0 - ban defines the bank to be precharged. if ap is l ow, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0 - ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0 - b a n inputs. if ap is low, then ba0 - b a n are used to define which bank to precharge. dq0 C dq 63 input - data input/output pins. cb0 C cb7 i/o - check bits are used for ecc. v dd , v ddspd , v ss supply - power supplies for core, i/o, serial presence detect, temp sensor, and ground for the module. v ref dq, v ref ca supply - reference voltage for sstl15 inputs . sda i/o - this is a bidirectional pin used to transfer data into or out of the spd eeprom and temp sensor. a resistor must be connected from the sda bus line to v ddspd on the system planar to act as a pull up. scl input - this signal is used to clock data into and out of the spd eeprom and temp sensor. sa0 C sa2 input - address pins used to select the serial presence detect and temp sensor base address. ????? ? out put - the ????? pin is reserved for use to flag critical module temperature. ????? ? input - this signal resets the ddr3 sdram . par_in ? input - parity bit for the address and control bus. ??????? ? out put - parity error detected on the address and control bus. a resistor may be connected from bus line to v dd on the system planar to act as a pull up.
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 5 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 1 of 2) [ 2 g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] d 8 n o t e s : 1 . d q - t o - i / o w i r i n g i s s h o w n a s r e c o m m e n d e d b u t m a y b e c h a n g e d . 2 . z q r e s i s t o r s a r e 2 4 0 1 % . f o r a l l o t h e r r e s i s t o r v a l u e s r e f e r t o t h e a p p r o p r i a t e w i r i n g d i a g r a m . z q v d d s p d v t t v r e f d q v r e f c a v d d s p d d 0 - d 8 d 0 - d 8 d 0 - d 8 v s s d 0 - d 8 d q s ? ? ? d q s 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 a ? ? ? ? ? r c k e 0 a r o d t 0 a a [ 1 4 : 0 ] a / b a [ 2 : 0 ] a ? ? ? ? d m 8 / d q s 1 7 ? ? ? ? ? c b [ 7 : 0 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 3 z q d q s ? ? ? d q s 3 ? ? ? ? d m 3 / d q s 1 2 ? ? ? ? ? d q [ 3 1 : 2 4 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 z q d q s ? ? ? d q s 2 ? ? ? ? d m 2 / d q s 1 1 ? ? ? ? ? d q [ 2 3 : 1 6 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 z q d q s ? ? ? d q s 1 ? ? ? ? d m 1 / d q s 1 0 ? ? ? ? ? d q [ 1 5 : 8 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 0 z q d q s ? ? ? d q s 0 ? ? ? ? d m 0 / d q s 9 ? ? ? ? d q [ 7 : 0 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k e o d t d 4 z q d q s ? ? ? d q s 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 a ? ? ? ? ? r c k e 0 b r o d t 0 b a [ 1 4 : 0 ] b / b a [ 2 : 0 ] b ? ? ? ? d m 4 / d q s 1 3 ? ? ? ? ? d q [ 3 9 : 3 2 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 5 z q d q s ? ? ? d q s 5 ? ? ? ? d m 5 / d q s 1 4 ? ? ? ? ? d q [ 4 7 : 4 0 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 z q d q s ? ? ? d q s 6 ? ? ? ? d m 6 / d q s 1 5 ? ? ? ? ? d q [ 5 5 : 4 8 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 7 z q d q s ? ? ? d q s 7 ? ? ? ? d m 7 / d q s 1 6 ? ? ? ? ? d q [ 6 3 : 5 6 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k e o d t v t t v t t d 0 - d 8 s p d w / i n t e g r a t e d t h e r m a l s e n s o r s c l ? ? ? ? ? s c l s d a ? ? ? ? ? s a 0 s a 1 a 0 a 1 a 2 s a 2 a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] c k ? ? c k ? ?
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 6 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 2 of 2) [ 2 g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] r e g i s t e r / p l l ? ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d 8 ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] b a [ 2 : 0 ] r b a [ 2 : 0 ] a b a [ 2 : 0 ] : s d r a m s d [ 3 : 0 ] , d 8 r b a [ 2 : 0 ] b b a [ 2 : 0 ] : s d r a m s d [ 7 : 4 ] a [ 1 4 : 0 ] r a [ 1 4 : 0 ] a a [ 1 4 : 0 ] : s d r a m s d [ 3 : 0 ] , d 8 r a [ 1 4 : 0 ] b a [ 1 4 : 0 ] : s d r a m s d [ 7 : 4 ] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d 8 ? ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d 8 ? ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d 8 ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] c k e 0 r c k e 0 a c k e 0 : s d r a m s d [ 3 : 0 ] , d 8 r c k e 0 b c k e 0 : s d r a m s d [ 7 : 4 ] r o d t 0 a o d t 0 : s d r a m s d [ 3 : 0 ] , d 8 r o d t 0 b o d t 0 : s d r a m s d [ 7 : 4 ] o d t 0 c k 0 ? ? ? p c k 0 a c k : s d r a m s d [ 3 : 0 ] , d 8 p c k 0 b c k : s d r a m s d [ 7 : 4 ] ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d 8 ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] c k 1 ? ? ? p a r _ i n ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 8 : 0 ] 1 2 0 1 % 1 2 0 5 % ? ? ? ? ? ? ? ? ? ? ? ? n o t e : s [ 3 : 2 ] , c k e 1 , o d t 1 a r e n c ( u n u s e d r e g i s t e r i n p u t s o d t 1 a n d c k e 1 h a v e a 3 3 0 r e s i s t o r t o g r o u n d )
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 7 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 1 of 2) [ 4 g b C 2 r ank s , 256 mx 8 ddr 3 sdrams ] d 8 n o t e s : 1 . d q - t o - i / o w i r i n g i s s h o w n a s r e c o m m e n d e d b u t m a y b e c h a n g e d . 2 . z q r e s i s t o r s a r e 2 4 0 1 % . f o r a l l o t h e r r e s i s t o r v a l u e s r e f e r t o t h e a p p r o p r i a t e w i r i n g d i a g r a m . 3 . u n l e s s o t h e r w i s e n o t e d , r e s i s t o r v a l u e s a r e 1 5 5 % . 4 . s e e t h e w i r i n g d i a g r a m s f o r a l l r e s i s t o r s a s s o c i a t e d w i t h t h e c o m m a n d , a d d r e s s a n d c o n t r o l b u s . z q v d d s p d v t t v r e f d q v r e f c a v d d s p d d 0 - d 1 7 d 0 - d 1 7 d 0 - d 1 7 v s s d 0 - d 1 7 d q s ? ? ? d q s 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 a ? ? ? ? ? r c k e 0 a r o d t 0 a a [ 1 4 : 0 ] a / b a [ 2 : 0 ] a ? ? ? ? d m 8 / d q s 1 7 ? ? ? ? ? c b [ 7 : 0 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 d q s ? ? ? d q s 3 ? ? ? ? d m 3 / d q s 1 2 ? ? ? ? ? d q [ 3 1 : 2 4 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 d q s ? ? ? d q s 2 ? ? ? ? d m 2 / d q s 1 1 ? ? ? ? ? d q [ 2 3 : 1 6 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 d q s ? ? ? d q s 1 ? ? ? ? d m 1 / d q s 1 0 ? ? ? ? ? d q [ 1 5 : 8 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 0 d q s ? ? ? d q s 0 ? ? ? ? d m 0 / d q s 9 ? ? ? ? d q [ 7 : 0 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t d 0 - d 1 7 s p d w / i n t e g r a t e d t h e r m a l s e n s o r s c l ? ? ? ? ? s c l s d a ? ? ? ? ? s a 0 s a 1 a 0 a 1 a 2 s a 2 z q z q z q z q d 1 7 z q d q s ? ? ? ? ? ? ? p c k 1 a ? ? ? ? ? r c k e 1 a r o d t 1 a t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 2 z q d q s ? ? ? t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 1 z q d q s ? ? ? t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 0 z q d q s ? ? ? t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 9 z q d q s ? ? ? t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 4 z q d q s ? ? ? d q s 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 b ? ? ? ? ? r c k e 0 b r o d t 0 b a [ 1 4 : 0 ] b / b a [ 2 : 0 ] b ? ? ? ? d m 4 / d q s 1 3 ? ? ? ? ? d q [ 3 9 : 3 2 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 5 d q s ? ? ? d q s 5 ? ? ? ? d m 5 / d q s 1 4 ? ? ? ? ? d q [ 4 7 : 4 0 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 d q s ? ? ? d q s 6 ? ? ? ? d m 6 / d q s 1 5 ? ? ? ? ? d q [ 5 5 : 4 8 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 7 d q s ? ? ? d q s 7 ? ? ? ? d m 7 / d q s 1 6 ? ? ? ? ? d q [ 6 3 : 5 6 ] t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k e o d t v t t z q z q z q d 1 3 z q d q s ? ? ? ? ? ? ? p c k 1 b ? ? ? ? ? r c k e 1 b r o d t 1 b t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 4 z q d q s ? ? ? t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 5 z q d q s ? ? ? t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 6 z q d q s ? ? ? t d q s ? ? ? ? d q [ 7 : 0 ] ? ? ? ? ? ? ? ? ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] c k ? ? c k ? ?
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 8 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 2 of 2) [ 4 g b C 2 r ank s , 256 mx 8 ddr 3 sdrams ] r e g i s t e r / p l l ? ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d 8 ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] b a [ 2 : 0 ] r b a [ 2 : 0 ] a b a [ 2 : 0 ] : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 r b a [ 2 : 0 ] b b a [ 2 : 0 ] : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] a [ 1 4 : 0 ] r a [ 1 4 : 0 ] a a [ 1 4 : 0 ] : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 r a [ 1 4 : 0 ] b a [ 1 4 : 0 ] : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] c k e 0 r c k e 0 a c k e 0 : s d r a m s d [ 3 : 0 ] , d 8 r c k e 0 b c k e 0 : s d r a m s d [ 7 : 4 ] r o d t 0 a o d t 0 : s d r a m s d [ 3 : 0 ] , d 8 r o d t 0 b o d t 0 : s d r a m s d [ 7 : 4 ] o d t 0 c k 0 ? ? ? p c k 0 a c k : s d r a m s d [ 3 : 0 ] , d 8 p c k 0 b c k : s d r a m s d [ 7 : 4 ] ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d 8 ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] c k 1 ? ? ? p a r _ i n ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 1 7 : 0 ] 1 2 0 1 % 1 2 0 5 % ? ? ? ? ? ? ? ? ? ? ? ? c k e 1 ? ? ? ? ? ? ? : s d r a m s d [ 1 2 : 9 ] , d 1 7 ? ? ? ? ? ? ? : s d r a m s d [ 1 6 : 1 3 ] r c k e 1 a c k e 1 : s d r a m s d [ 1 2 : 9 ] , d 1 7 r c k e 1 b c k e 1 : s d r a m s d [ 1 6 : 1 3 ] r o d t 1 a o d t 1 : s d r a m s d [ 1 2 : 9 ] , d 1 7 r o d t 1 b o d t 1 : s d r a m s d [ 1 6 : 1 3 ] o d t 1 p c k 1 a c k : s d r a m s d [ 1 2 : 9 ] , d 1 7 p c k 1 b c k : s d r a m s d [ 1 6 : 1 3 ] ? ? ? ? ? ? ? : s d r a m s d [ 1 2 : 9 ] , d 1 7 ? ? ? ? ? ? ? : s d r a m s d [ 1 6 : 1 3 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 9 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 1 of 3) [4g b C 1 r ank, 512 mx 4 ddr 3 sdrams ] d 8 z q d q s ? ? ? d q s 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 a ? ? ? ? ? r c k e 0 a r o d t 0 a a [ 1 4 : 0 ] a b a [ 2 : 0 ] a ? ? ? ? c b [ 3 : 0 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 3 z q d q s ? ? ? d q s 3 ? ? ? ? d q [ 2 7 : 2 4 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 2 z q d q s ? ? ? d q s 2 ? ? ? ? d q [ 1 9 : 1 6 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 1 z q d q s ? ? ? d q s 1 ? ? ? ? d q [ 1 1 : 8 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 0 z q d q s ? ? ? d q s 0 ? ? ? ? d q [ 3 : 0 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 1 7 z q d q s ? ? ? d q s 1 7 ? ? ? ? ? c b [ 7 : 4 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 1 2 z q d q s ? ? ? d q s 1 2 ? ? ? ? ? d q [ 3 1 : 2 8 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 1 1 z q d q s ? ? ? d q s 1 1 ? ? ? ? ? d q [ 2 3 : 2 0 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 1 0 z q d q s ? ? ? d q s 1 0 ? ? ? ? ? d q [ 1 5 : 1 2 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] v t t d 9 z q d q s ? ? ? d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d q s 9 ? ? ? ? d q [ 7 : 4 ] d m v s s d m v s s d m v s s d m v s s d m v s s d m v s s d m v s s d m v s s d m v s s d m v s s ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 a ? ? ? ? ? r c k e 0 a r o d t 0 a a [ 1 4 : 0 ] a b a [ 2 : 0 ] a
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 10 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 2 of 3) [ 4g b C 1 r ank, 512 mx 4 ddr 3 sdrams ] d 4 z q d q s ? ? ? d q s 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 b ? ? ? ? ? r c k e 0 b r o d t 0 b a [ 1 4 : 0 ] b b a [ 2 : 0 ] b ? ? ? ? d q [ 3 5 : 3 2 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 1 4 : 0 ] b a [ 2 : 0 ] d 5 z q d q s ? ? ? d q s 5 ? ? ? ? d q [ 4 3 : 4 0 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 z q d q s ? ? ? d q s 6 ? ? ? ? d q [ 5 1 : 4 8 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 7 z q d q s ? ? ? d q s 7 ? ? ? ? d q [ 5 9 : 5 6 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 3 z q d q s ? ? ? d q s 1 3 ? ? ? ? ? d q [ 3 9 : 3 6 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 4 z q d q s ? ? ? d q s 1 4 ? ? ? ? ? d q [ 4 7 : 4 4 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 5 z q d q s ? ? ? d q s 1 5 ? ? ? ? ? d q [ 5 5 : 5 2 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 6 z q d q s ? ? ? d q s 1 6 ? ? ? ? ? d q [ 6 3 : 6 0 ] d q [ 4 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t v d d s p d v t t v r e f d q v r e f c a v d d s p d d 0 - d 1 7 d 0 - d 1 7 d 0 - d 1 7 v s s d 0 - d 1 7 d 0 - d 1 7 s p d w / i n t e g r a t e d t h e r m a l s e n s o r s c l ? ? ? ? ? s c l s d a ? ? ? ? ? s a 0 s a 1 a 0 a 1 a 2 s a 2 n o t e s : 1 . d q - t o - i / o w i r i n g i s s h o w n a s r e c o m m e n d e d b u t m a y b e c h a n g e d . 2 . z q r e s i s t o r s a r e 2 4 0 1 % . f o r a l l o t h e r r e s i s t o r v a l u e s r e f e r t o t h e a p p r o p r i a t e w i r i n g d i a g r a m . 3 . u n l e s s o t h e r w i s e n o t e d , r e s i s t o r v a l u e s a r e 1 5 5 % . 4 . s e e t h e w i r i n g d i a g r a m s f o r a l l r e s i s t o r s a s s o c i a t e d w i t h t h e c o m m a n d , a d d r e s s a n d c o n t r o l b u s . a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] d m v s s d m v s s d m v s s d m v s s d m v s s d m v s s d m v s s d m v s s ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 b ? ? ? ? ? r c k e 0 b r o d t 0 b a [ 1 4 : 0 ] b b a [ 2 : 0 ] b
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 11 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 3 of 3) [ 4g b C 1 r ank, 512 mx 4 ddr 3 sdrams ] r e g i s t e r / p l l ? ? ? ? ? c s 0 _ a : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? c s 0 _ b : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] b a [ 2 : 0 ] b a [ 2 : 0 ] a b a [ 2 : 0 ] : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 b a [ 2 : 0 ] b b a [ 2 : 0 ] : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] a [ 1 4 : 0 ] a a [ 1 4 : 0 ] b ? ? ? ? ? ? ? ? ? ? ? ? ? r a s : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? r a s : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] ? ? ? ? ? c a s : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? c a s : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] ? ? ? ? w e : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? w e : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] c k e 0 r c k e 0 a c k e 0 : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 r c k e 0 b c k e 0 : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] r o d t 0 a o d t 0 : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 r o d t 0 b o d t 0 : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] o d t 0 c k 0 ? ? ? p c k 0 a c k : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 p c k 0 b c k : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] ? ? ? ? ? c k : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? c k : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] c k 1 ? ? ? p a r _ i n ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 1 7 : 0 ] 1 2 0 1 % 1 2 0 5 % ? ? ? ? ? ? ? ? ? ? ? ? c k e 1 o d t 1 ? ? ? ? a [ 1 4 : 0 ] a [ 1 4 : 0 ] : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 a [ 1 4 : 0 ] : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 12 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram ( p art 1 of 3 ) [ 8 g b C 2 r ank s , 512 mx 4 ddr 3 sdrams ] d 1 7 d m d q s ? ? ? d q s 1 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 a ? ? ? ? ? r c k e 0 a r o d t 0 a a [ 1 4 : 0 ] a / b a [ 2 : 0 ] a ? ? ? ? ? v s s c b [ 7 : 4 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t d 3 5 d q s ? ? ? ? ? ? ? p c k 1 a ? ? ? ? ? r c k e 1 a r o d t 1 a ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 a ? ? ? ? ? r c k e 0 a r o d t 0 a a [ 1 4 : 0 ] a / b a [ 2 : 0 ] a ? ? ? ? p c k 1 a ? ? ? ? ? r c k e 1 a r o d t 1 a d m d q [ 3 : 0 ] d q s 1 2 ? ? ? ? ? v s s d q [ 3 1 : 2 8 ] d m d q [ 3 : 0 ] d m d q [ 3 : 0 ] d 1 1 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 9 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s 1 1 ? ? ? ? ? v s s d q [ 2 3 : 2 0 ] d m d q [ 3 : 0 ] d m d q [ 3 : 0 ] d 1 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 8 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s 1 0 ? ? ? ? ? v s s d q [ 1 5 : 1 2 ] d m d q [ 3 : 0 ] d m d q [ 3 : 0 ] d 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 8 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s 0 ? ? ? ? v s s d q [ 3 : 0 ] d m d q [ 3 : 0 ] d m d q [ 3 : 0 ] d 8 d m d q s ? ? ? d q s 8 ? ? ? ? v s s c b [ 3 : 0 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 6 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] d 3 d m d q s ? ? ? d q s 3 ? ? ? ? v s s d q [ 2 7 : 2 4 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 1 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] d 2 d m d q s ? ? ? d q s 2 ? ? ? ? v s s d q [ 1 9 : 1 6 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] d 1 d m d q s ? ? ? d q s 1 ? ? ? ? v s s d q [ 1 1 : 8 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 9 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] d 9 d m d q s ? ? ? d q s 9 ? ? ? ? v s s d q [ 7 : 4 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 7 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 13 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram ( p art 2 of 3 ) [ 8 g b C 2 r ank s , 512 mx 4 ddr 3 sdrams ] d 1 4 n o t e s : 1 . d q - t o - i / o w i r i n g i s s h o w n a s r e c o m m e n d e d b u t m a y b e c h a n g e d . 2 . z q p i n s o f e a c h s d r a m a r e c o n n e c t e d t o i n d i v i d u a l r z q r e s i s t o r s ( 2 4 0 1 % ) . 3 . s e e t h e w i r i n g d i a g r a m s f o r r e s i s t o r v a l u e s . d m v d d s p d v t t v r e f d q v r e f c a v d d s p d d 0 - d 3 5 d 0 - d 3 5 d 0 - d 3 5 v s s d 0 - d 3 5 d q s ? ? ? d q s 1 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 b ? ? ? ? ? r c k e 0 b r o d t 0 b a [ 1 4 : 0 ] b / b a [ 2 : 0 ] b ? ? ? ? ? v s s d q [ 4 7 : 4 4 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t d 0 - d 3 5 s p d w / i n t e g r a t e d t h e r m a l s e n s o r s c l ? ? ? ? ? s c l s d a ? ? ? ? ? s a 0 s a 1 a 0 a 1 a 2 s a 2 d 2 2 d q s ? ? ? ? ? ? ? p c k 1 b ? ? ? ? ? r c k e 1 b r o d t 1 b ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p c k 0 b ? ? ? ? ? r c k e 0 b r o d t 0 b a [ 1 4 : 0 ] b / b a [ 2 : 0 ] b ? ? ? ? p c k 1 b ? ? ? ? ? r c k e 1 b r o d t 1 b d m d q [ 3 : 0 ] d q s 4 ? ? ? ? v s s d q [ 3 5 : 3 2 ] d m d q [ 3 : 0 ] d m d q [ 3 : 0 ] d 1 6 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s 1 6 ? ? ? ? ? v s s d q [ 6 3 : 6 0 ] d m d q [ 3 : 0 ] d m d q [ 3 : 0 ] d 7 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 5 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s 7 ? ? ? ? v s s d q [ 5 9 : 5 6 ] d m d q [ 3 : 0 ] d m d q [ 3 : 0 ] d 1 3 d m d q s ? ? ? d q s 1 3 ? ? ? ? ? v s s d q [ 3 9 : 3 6 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 1 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] d 5 d m d q s ? ? ? d q s 5 ? ? ? ? v s s d q [ 4 3 : 4 0 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 3 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] d 1 5 d m d q s ? ? ? d q s 1 5 ? ? ? ? ? v s s d q [ 5 5 : 5 2 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 3 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] d 6 d m d q s ? ? ? d q s 6 ? ? ? ? v s s d q [ 5 1 : 4 8 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] v t t a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 14 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 3 of 3) [ 8 g b C 2 r ank s , 512 mx 4 ddr 3 sdrams ] r e g i s t e r / p l l ? ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? ? ? : s d r a m s d [ 2 5 : 2 1 ] , d [ 3 4 : 3 1 ] b a [ 2 : 0 ] r b a [ 2 : 0 ] a b a [ 2 : 0 ] : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d [ 2 1 : 1 7 ] , d [ 3 0 : 2 6 ] , d 3 5 r b a [ 2 : 0 ] b b a [ 2 : 0 ] : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] , d [ 2 5 : 2 2 ] , d [ 3 4 : 3 1 ] a [ 1 4 : 0 ] r a [ 1 4 : 0 ] a a [ 1 4 : 0 ] : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d [ 2 1 : 1 7 ] , d [ 3 0 : 2 6 ] , d 3 5 r a [ 1 4 : 0 ] b a [ 1 4 : 0 ] : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] , d [ 2 5 : 2 2 ] , d [ 3 4 : 3 1 ] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d [ 2 1 : 1 7 ] , d [ 3 0 : 2 6 ] , d 3 5 ? ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] , d [ 2 5 : 2 2 ] , d [ 3 4 : 3 1 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d [ 2 1 : 1 7 ] , d [ 3 0 : 2 6 ] , d 3 5 ? ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] , d [ 2 5 : 2 2 ] , d [ 3 4 : 3 1 ] ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d [ 2 1 : 1 7 ] , d [ 3 0 : 2 6 ] , d 3 5 ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] , d [ 2 5 : 2 2 ] , d [ 3 4 : 3 1 ] c k e 0 r c k e 0 a c k e 0 : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 r c k e 0 b c k e 0 : s d r a m s d [ 2 5 : 2 2 ] , d [ 3 4 : 3 1 ] r o d t 0 a o d t 0 : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 r o d t 0 b o d t 0 : s d r a m s d [ 7 : 4 ] , d [ 3 4 : 3 1 ] o d t 0 c k 0 ? ? ? p c k 0 a c k : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 p c k 0 b c k : s d r a m s d [ 2 5 : 2 2 ] , d [ 3 4 : 3 1 ] ? ? ? ? ? ? ? : s d r a m s d [ 3 : 0 ] , d [ 1 2 : 8 ] , d 1 7 ? ? ? ? ? ? ? : s d r a m s d [ 2 5 : 2 2 ] , d [ 3 4 : 3 1 ] c k 1 ? ? ? p a r _ i n ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 1 7 : 0 ] , d [ 3 5 : 1 8 ] 1 2 0 1 % 1 2 0 5 % ? ? ? ? ? ? ? ? ? ? ? ? c k e 1 ? ? ? ? ? ? ? : s d r a m s d [ 2 1 : 1 8 ] b , d [ 3 0 : 2 6 ] , d 3 5 ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] r c k e 1 a c k e 1 : s d r a m s d [ 2 1 : 1 8 ] , d [ 3 0 : 2 6 ] , d 3 5 r c k e 1 b c k e 1 : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] r o d t 1 a o d t 1 : s d r a m s d [ 2 1 : 1 8 ] , d [ 3 0 : 2 6 ] , d 3 5 r o d t 1 b o d t 1 : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] o d t 1 p c k 1 a c k : s d r a m s d [ 2 1 : 1 8 ] , d [ 3 0 : 2 6 ] , d 3 5 p c k 1 b c k : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ] ? ? ? ? ? ? ? : s d r a m s d [ 2 1 : 1 8 ] , d [ 3 0 : 2 6 ] , d 3 5 ? ? ? ? ? ? ? : s d r a m s d [ 7 : 4 ] , d [ 1 6 : 1 3 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 15 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 1 of 5 ) [ 16 g b C 4 r ank s , 1g x4 (ddp) ddr 3 sdrams ] d 9 d m d q s ? ? ? d q s 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a p c k 0 a ? ? ? ? ? ? a r c k e 0 a a r o d t 0 a a r a [ 1 4 : 0 ] a / a r b a [ 2 : 0 ] a ? ? ? ? v s s c b [ 3 : 0 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t d 8 d q s ? ? ? ? ? ? ? ? a r c k e 1 a v d d ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b p c k 0 a ? ? ? ? ? ? b r c k e 0 a b r o d t 1 a b r a [ 1 4 : 0 ] a / b r b a [ 2 : 0 ] a d m d q [ 3 : 0 ] z q z q v s s v s s d 7 d m d q s ? ? ? d q s 3 ? ? ? ? v s s d q [ 2 7 : 2 4 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 5 d m d q s ? ? ? d q s 2 ? ? ? ? v s s d q [ 1 9 : 1 6 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 3 d m d q s ? ? ? d q s 1 ? ? ? ? v s s d q [ 1 1 : 8 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 1 d m d q s ? ? ? d q s 0 ? ? ? ? v s s d q [ 3 : 0 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 4 5 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 4 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 4 7 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 4 6 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 4 9 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 4 8 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 5 1 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 5 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s d 5 3 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 5 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s ? ? ? ? ? b r c k e 1 a v d d v s s a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 16 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 2 of 5 ) [ 16g b C 4 r ank s , 1g x4 (ddp) ddr 3 sdrams ] d 2 7 d m d q s ? ? ? d q s 1 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a p c k 1 a ? ? ? ? ? ? a r c k e 0 a a r o d t 0 a a r a [ 1 4 : 0 ] a / a r b a [ 2 : 0 ] a ? ? ? ? ? v s s c b [ 7 : 4 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t d 2 6 d q s ? ? ? ? ? ? ? ? a r c k e 1 a v d d ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b p c k 1 a ? ? ? ? ? ? b r c k e 0 a b r o d t 1 a b r a [ 1 4 : 0 ] a / b r b a [ 2 : 0 ] a d m d q [ 3 : 0 ] z q z q v s s v s s d 2 5 d m d q s ? ? ? d q s 1 2 ? ? ? ? ? v s s d q [ 3 1 : 2 8 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 2 3 d m d q s ? ? ? d q s 1 1 ? ? ? ? ? v s s d q [ 2 3 : 2 0 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 2 1 d m d q s ? ? ? d q s 1 0 ? ? ? ? ? v s s d q [ 1 5 : 1 2 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 2 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 1 9 d m d q s ? ? ? d q s 9 ? ? ? ? v s s d q [ 7 : 4 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 8 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 6 3 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 6 5 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 6 7 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 6 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 6 9 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 8 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s d 7 1 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 7 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s ? ? ? ? ? b r c k e 1 a v d d v s s a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 17 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 3 of 5 ) [ 16g b C 4 r ank s , 1g x4 (ddp) ddr 3 sdrams ] d 1 1 d m d q s ? ? ? d q s 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a p c k 0 b ? ? ? ? ? ? a r c k e 0 b a r o d t 0 b a r a [ 1 4 : 0 ] b / a r b a [ 2 : 0 ] b ? ? ? ? v s s d q [ 3 5 : 3 2 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t d 1 0 d q s ? ? ? ? ? ? ? ? a r c k e 1 b v d d ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b p c k 0 b ? ? ? ? ? ? b r c k e 0 b b r o d t 1 b b r a [ 1 4 : 0 ] b / b r b a [ 2 : 0 ] b d m d q [ 3 : 0 ] z q z q v s s v s s d 1 3 d m d q s ? ? ? d q s 5 ? ? ? ? v s s d q [ 4 3 : 4 0 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 1 5 d m d q s ? ? ? d q s 6 ? ? ? ? v s s d q [ 5 1 : 4 8 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 1 7 d m d q s ? ? ? d q s 7 ? ? ? ? v s s d q [ 5 9 : 5 6 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 1 6 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 4 3 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 4 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 4 1 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 4 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 3 9 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 8 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 3 7 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 6 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s ? ? ? ? ? b r c k e 1 b v d d v s s a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 18 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 4 of 5 ) [ 16g b C 4 r ank s , 1g x4 (ddp) ddr 3 sdrams ] d 2 9 d m d q s ? ? ? d q s 1 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a p c k 1 b ? ? ? ? ? ? a r c k e 0 b a r o d t 0 b a r a [ 1 4 : 0 ] b / a r b a [ 2 : 0 ] b ? ? ? ? ? v s s d q [ 3 9 : 3 6 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t v t t d 2 8 d q s ? ? ? ? ? ? ? ? a r c k e 1 b v d d ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b p c k 1 b ? ? ? ? ? ? b r c k e 0 b b r o d t 1 b b r a [ 1 4 : 0 ] b / b r b a [ 2 : 0 ] b d m d q [ 3 : 0 ] z q z q v s s v s s d 3 1 d m d q s ? ? ? d q s 1 4 ? ? ? ? ? v s s d q [ 4 7 : 4 4 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 3 3 d m d q s ? ? ? d q s 1 5 ? ? ? ? ? v s s d q [ 5 5 : 5 2 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 2 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 3 5 d m d q s ? ? ? d q s 1 6 ? ? ? ? ? v s s d q [ 6 3 : 6 0 ] d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 3 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 6 1 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 6 0 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 5 9 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 5 8 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 5 7 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 5 6 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s v s s d 5 5 d m d q s ? ? ? d q [ 3 : 0 ] ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d 5 4 d q s ? ? ? ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d m d q [ 3 : 0 ] z q z q v s s ? ? ? ? ? b r c k e 1 b v d d v s s n o t e s : 1 . d q - t o - i / o w i r i n g i s m a y b e c h a n g e d w i t h i n a n i b b l e . 2 , r e s i s t o r v a l u e s a r e 1 5 5 % . 2 . z q r e s i s t o r s a r e 2 4 0 1 % . 3 . s e e t h e w i r i n g d i a g r a m s f o r r e s i s t o r v a l u e s . v d d s p d v t t v r e f d q v r e f c a v d d s p d d 0 - d 7 1 d 0 - d 7 1 d 0 - d 7 1 v s s d 0 - d 7 1 d 0 - d 7 1 s p d w / i n t e g r a t e d t h e r m a l s e n s o r s c l ? ? ? ? ? s c l s d a ? ? ? ? ? s a 0 s a 1 a 0 a 1 a 2 s a 2 a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ] a [ 1 4 : 0 ] b a [ 2 : 0 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 19 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (part 5 of 5) [ 16g b C 4 r ank s , 1g x4 (ddp) ddr 3 sdrams ] r e g i s t e r / p l l a ? ? ? ? ? ? ? ? ? ? ? ? : s d r a m s d 1 , d 3 , d 5 , d 7 , d 9 , d 1 9 , d 2 1 , d 2 3 , d 2 5 , d 2 7 ? ? ? ? ? ? ? ? : s d r a m s d 1 1 , d 1 3 , d 1 5 , d 1 7 , d 2 9 , d 3 1 , d 3 3 , d 3 5 b a [ 2 : 0 ] a r b a [ 2 : 0 ] a b a [ 2 : 0 ] : s d r a m s d [ 9 : 0 ] , d [ 2 7 : 1 8 ] a r b a [ 2 : 0 ] b b a [ 2 : 0 ] : s d r a m s d [ 1 7 : 1 0 ] , d [ 3 5 : 2 8 ] a [ 1 4 : 0 ] a r a [ 1 4 : 0 ] a a [ 1 4 : 0 ] : s d r a m s d [ 9 : 0 ] , d [ 2 7 : 1 8 ] a r a [ 1 4 : 0 ] b a [ 1 4 : 0 ] : s d r a m s d [ 1 7 : 1 0 ] , d [ 3 5 : 2 8 ] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 9 : 0 ] , d [ 2 7 : 1 8 ] ? ? ? ? ? ? ? ? ? : s d r a m s d [ 1 7 : 1 0 ] , d [ 3 5 : 2 8 ] ? ? ? ? ? ? ? ? ? : s d r a m s d [ 9 : 0 ] , d [ 2 7 : 1 8 ] ? ? ? ? ? ? ? ? ? : s d r a m s d [ 1 7 : 1 0 ] , d [ 3 5 : 2 8 ] ? ? ? ? ? ? ? : s d r a m s d [ 9 : 0 ] , d [ 2 7 : 1 8 ] ? ? ? ? ? ? ? : s d r a m s d [ 1 7 : 1 0 ] , d [ 3 5 : 2 8 ] c k e 0 a r c k e 0 a c k e 1 : s d r a m s d 1 , d 3 , d 5 , d 7 , d 9 , d 1 9 , d 2 1 , d 2 3 , d 2 5 , d 2 7 a r c k e 0 b c k e 1 : s d r a m s d 1 1 , d 1 3 , d 1 5 , d 1 7 , d 2 9 , d 3 1 , d 3 3 , d 3 5 a r o d t 0 a o d t 1 : s d r a m s d 1 , d 3 , d 5 , d 7 , d 9 , d 1 9 , d 2 1 , d 2 3 , d 2 5 , d 2 7 a r o d t 0 b o d t 1 : s d r a m s d 1 1 , d 1 3 , d 1 5 , d 1 7 , d 2 9 , d 3 1 , d 3 3 , d 3 5 o d t 0 c k 0 ? ? ? a p c k 0 a c k : s d r a m s d [ 9 : 0 ] a p c k 0 b c k : s d r a m s d [ 1 7 : 1 0 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 9 : 0 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 1 7 : 1 0 ] c k 1 ? ? ? p a r _ i n ? ? ? ? ? ? ? ? ? ? : s d r a m s d [ 7 1 : 0 ] 1 2 0 1 % 1 2 0 5 % ? ? ? ? ? ? ? ? ? ? ? ? c k e 1 ? ? ? ? ? ? ? ? : s d r a m s d 0 , d 2 , d 4 , d 6 , d 8 , d 1 8 , d 2 0 , d 2 2 , d 2 4 , d 2 6 ? ? ? ? ? ? ? ? : s d r a m s d 1 0 , d 1 2 , d 1 4 , d 1 6 , d 2 8 , d 3 0 , d 3 2 , d 3 4 a r c k e 1 a c k e 0 : s d r a m s d 0 , d 2 , d 4 , d 6 , d 8 , d 1 8 , d 2 0 , d 2 2 , d 2 4 , d 2 6 a r c k e 1 b c k e 0 : s d r a m s d 1 0 , d 1 2 , d 1 4 , d 1 6 , d 2 8 , d 3 0 , d 3 2 , d 3 4 a p c k 1 a c k : s d r a m s d [ 2 7 : 1 8 ] a p c k 1 b c k : s d r a m s d [ 3 5 : 2 8 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 2 7 : 1 8 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 3 5 : 2 8 ] r e g i s t e r / p l l b ? ? ? ? b a [ 2 : 0 ] a [ 1 4 : 0 ] ? ? ? ? ? ? ? ? c k e 0 c k 0 ? ? ? c k 1 ? ? ? p a r _ i n ? ? ? ? ? ? ? 1 2 0 1 % 1 2 0 5 % ? ? ? ? ? ? ? ? ? ? ? ? c k e 1 o d t 1 ? ? ? ? ? ? ? ? : s d r a m s d 4 5 , d 4 7 , d 4 9 , d 5 1 , d 5 3 , d 6 3 , d 6 5 , d 6 7 , d 6 9 , d 7 1 ? ? ? ? ? ? ? ? : s d r a m s d 3 7 , d 3 9 , d 4 1 , d 4 3 , d 5 5 , d 5 7 , d 5 9 , d 6 1 b r b a [ 2 : 0 ] a b a [ 2 : 0 ] : s d r a m s d [ 5 3 : 4 4 ] , d [ 7 1 : 6 2 ] b r b a [ 2 : 0 ] b b a [ 2 : 0 ] : s d r a m s d [ 4 3 : 3 6 ] , d [ 6 1 : 5 4 ] b r a [ 1 4 : 0 ] a a [ 1 4 : 0 ] : s d r a m s d [ 5 3 : 4 4 ] , d [ 7 1 : 6 2 ] b r a [ 1 4 : 0 ] b a [ 1 4 : 0 ] : s d r a m s d [ 4 3 : 3 6 ] , d [ 6 1 : 5 4 ] ? ? ? ? ? ? ? ? ? : s d r a m s d [ 5 3 : 4 4 ] , d [ 7 1 : 6 2 ] ? ? ? ? ? ? ? ? ? : s d r a m s d [ 4 3 : 3 6 ] , d [ 6 1 : 5 4 ] ? ? ? ? ? ? ? ? ? : s d r a m s d [ 5 3 : 4 4 ] , d [ 7 1 : 6 2 ] ? ? ? ? ? ? ? ? ? : s d r a m s d [ 4 3 : 3 6 ] , d [ 6 1 : 5 4 ] ? ? ? ? ? ? ? : s d r a m s d [ 5 3 : 4 4 ] , d [ 7 1 : 6 2 ] ? ? ? ? ? ? ? : s d r a m s d [ 4 3 : 3 6 ] , d [ 6 1 : 5 4 ] b r c k e 0 a c k e 1 : s d r a m s d 4 5 , d 4 7 , d 4 9 , d 5 1 , d 5 3 , d 6 3 , d 6 5 , d 6 7 , d 6 9 , d 7 1 b r c k e 0 b c k e 1 : s d r a m s d 3 7 , d 3 9 , d 4 1 , d 4 3 , d 5 5 , d 5 7 , d 5 9 , d 6 1 b r o d t 0 a o d t 1 : s d r a m s d 4 5 , d 4 7 , d 4 9 , d 5 1 , d 5 3 , d 6 3 , d 6 5 , d 6 7 , d 6 9 , d 7 1 b r o d t 0 b o d t 1 : s d r a m s d 3 7 , d 3 9 , d 4 1 , d 4 3 , d 5 5 , d 5 7 , d 5 9 , d 6 1 b p c k 0 a c k : s d r a m s d [ 5 3 : 4 4 ] b p c k 0 b c k : s d r a m s d [ 4 3 : 3 6 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 5 3 : 4 4 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 4 3 : 3 6 ] ? ? ? ? ? ? ? ? : s d r a m s d 4 4 , d 4 6 , d 4 8 , d 5 0 , d 5 2 , d 6 2 , d 6 4 , d 6 6 , d 6 8 , d 7 0 ? ? ? ? ? ? ? ? : s d r a m s d 3 6 , d 3 8 , d 4 0 , d 4 2 , d 5 4 , d 5 6 , d 5 8 , d 6 0 b r c k e 1 a c k e 0 : s d r a m s d 4 4 , d 4 6 , d 4 8 , d 5 0 , d 5 2 , d 6 2 , d 6 4 , d 6 6 , d 6 8 , d 7 0 b r c k e 1 b c k e 0 : s d r a m s d 3 6 , d 3 8 , d 4 0 , d 4 2 , d 5 4 , d 5 6 , d 5 8 , d 6 0 b p c k 1 a c k : s d r a m s d [ 7 1 : 6 2 ] b p c k 1 b c k : s d r a m s d [ 6 1 : 5 4 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 7 1 : 6 2 ] ? ? ? ? ? ? ? ? : s d r a m s d [ 6 1 : 5 4 ]
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 20 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. environmental requirements symbol parameter rating units note h opr operating humidity (relative) 10 to 90 % 1 t stg storage temperature (plastic) - 55 to 100 c 1 h stg storage humidity (without condensation) 5 to 95 % 1 p bar barometric pressure (operating & storage) 105 to 69 k pascal 1, 2 note : 1 . stresses greater than those listed may cause permanent damage to the device. this is a s tress rating only and device functional operation at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect reliability. 2. up to 9850 ft . absolute maximum dc ratings symbol parameter rating units note v dd voltage on vdd pins relative to vss - 0.4 v ~ 1.975 v v 1, 3 v dd q voltage on vddq pins relative to vss - 0.4 v ~ 1.975 v v 1, 3 v in , v out voltage on i/o pins relative to vss - 0.4 v ~ 1.975 v v 1 t stg storage temperature - 55 to +100 c 1, 2 note : 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability 2. storage temperature is the case surface temperature on the center/top side of the dram. 3. vdd and vddq must be within 300 mv of each other at all times;and vref must be not greater operating temperature conditions symbol parameter rating units note t op e r normal operating temperature range 0 to 85 c 1, 2 extended temperature range (optional) 85 to 95 c 1, 3 note: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, the dram case temperature mus t be maintained between 0 to 85 c under all operating conditions 3. some applications require operation of the dram in the extended temperature range between 85 c and 95 c case temperature. full specifications are supported in this range, but the following additional conditions apply: a ) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extended temperature range. please refer to supplier data sheet and/or the dimm spd for option availability. b ) if self - refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self - refresh mode with extended temperature range ca pability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self - refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). please refer to the supplier data sheet and/or the dimm spd for auto self - refresh option availability, extended temperature range support an d trefi requirements in the extended temperature range.
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 21 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. dc electrical characteristics and operating conditions symbol parameter min type max units notes v dd supply voltage 1.425 1.5 1.575 v 1,2 v dd q output supply voltage 1.425 1.5 1.575 v 1,2 v dd supply voltage 1. 2 8 1. 3 5 1. 4 5 v ddr3l v dd q output supply voltage 1. 2 8 1. 3 5 1. 4 5 v ddr3l note: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. single - ended ac and dc input levels for command and address symbol parameter ddr3 - 1066 ( - be) ddr3 - 1333 ( - cg) units note min. max. min. max. v ih.ca(dc) dc input logic high vref + 0.100 vdd vref + 0.100 vdd v 1 v il .ca(dc) dc input logic low vss vref - 0.100 vss vref - 0.100 v 1 v ih.ca(ac) ac input logic high vref + 0.175 note 2 vref + 0.175 note 2 v 1, 2 v il .ca(ac) ac input logic low note 2 vref - 0.175 note 2 vref - 0.175 v 1, 2 v ih.ca(ac150) ac input logic high - - vref + 0.15 note 2 v 1, 2 v i l .ca(ac150) ac input logic low - - note 2 vref - 0.1 5 v 1, 2 v ref ca (dc) reference voltage for add, cmd inputs 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd v 3, 4 note: 1. for input only pins except ????? . vref = vrefca(dc). 2. see overshoot and undershoot specifications in the device datasheet . 3. the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 15 mv). 4. for reference: approx. vdd/2 +/ - 15 mv. single - ended ac and dc input levels for dq and dm symbol parameter ddr3 - 1066 ( - be) ddr3 - 1333 ( - cg) units note min. max. min. max. v ih.dq(dc) dc input logic high vref + 0.100 vdd vref + 0.100 vdd v 1 v il.dq(dc) dc input logic low vss vref - 0.100 vss vref - 0.100 v 1 v ih.dq(ac) ac input logic high vref + 0.175 note 2 vref + 0.1 5 note 2 v 1, 2, 5 v il.dq(ac) ac input logic low note 2 vref - 0.175 note 2 vref - 0.1 5 v 1, 2, 5 v ref dq (dc) reference voltage for dq, dm inputs 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd v 3, 4 note: 1. f or input only pins except ????? . vref = vrefdq(dc). 2. see overshoot and undershoot specifications in the device datasheet . 3. the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 15 mv). 4. for reference: approx. vdd/2 +/ - 15 mv. 5. single - ended swing requirement for dqs, dqs# is 350 mv (peak to peak). differential swing requirement for dqs - dqs# is 700 mv (peak to peak).
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 22 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1. 5v 0.075 v [ 2 g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 649 697 ma idd1 operating one bank active - read - precharge current 816 879 ma idd2p1 precharge power - down current fast exit 117 135 ma idd2q precharge quiet standby current 187 214 ma idd2n precharge standby current 205 238 ma idd3p active power - down current 128 145 ma idd3n active standby current 265 265 ma idd4r operating burst read current 1137 1370 ma idd4w operating burst write current 1156 1378 ma idd5b burst refresh current 1723 1733 ma idd6 self refresh current: normal temperature range 94 94 ma idd7 operating bank interleave read current 2914 3552 ma t case = 0 c ~ 85 c; v ddq = v dd = 1.35v - 0.0675/ + 0.1v [ 2 g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 634 673 ma idd1 operating one bank active - read - precharge current 780 836 ma idd2p1 precharge power - down current fast exit 103 117 ma idd2q precharge quiet standby current 157 177 ma idd2n precharge standby current 172 193 ma idd3p active power - down current 111 125 ma idd3n active standby current 2 28 228 ma idd4r operating burst read current 1119 1346 ma idd4w operating burst write current 1139 1356 ma idd5b burst refresh current 1663 1673 ma idd6 self refresh current: normal temperature range 74 74 ma idd7 operating bank interleave read current 2822 3406 ma
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 23 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. t case = 0 c ~ 85 c; v ddq = v dd = 1. 5v 0.075 v [ 4 g b C 2 r ank, 256 mx 8 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 915 962 ma idd1 operating one bank active - read - precharge current 1081 1144 ma idd2p1 precharge power - down current fast exit 235 269 ma idd2q precharge quiet standby current 375 428 ma idd2n precharge standby current 409 475 ma idd3p active power - down current 256 290 ma idd3n active standby current 531 531 ma idd4r operating burst read current 1402 1635 ma idd4w operating burst write current 1422 1643 ma idd5b burst refresh current 1988 1998 ma idd6 self refresh current: normal temperature range 187 187 ma idd7 operating bank interleave read current 3179 3817 ma t case = 0 c ~ 85 c; v ddq = v dd = 1.35v - 0.0675/ + 0.1v [ 4 g b C 2 r ank, 256 mx 8 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 863 902 ma idd1 operating one bank active - read - precharge current 1010 1064 ma idd2p1 precharge power - down current fast exit 206 235 ma idd2q precharge quiet standby current 314 354 ma idd2n precharge standby current 343 385 ma idd3p active power - down current 222 251 ma idd3n active standby current 45 7 457 ma idd4r operating burst read current 1348 1575 ma idd4w operating burst write current 1368 1585 ma idd5b burst refresh current 1893 1901 ma idd6 self refresh current: normal temperature range 148 148 ma idd7 operating bank interleave read current 3051 3634 ma
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 24 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. t case = 0 c ~ 85 c; v ddq = v dd = 1. 5v 0.075 v [ 4 g b C 1 r ank, 512 mx 4 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 1307 1402 ma idd1 operating one bank active - read - precharge current 1624 1734 ma idd2p1 precharge power - down current fast exit 285 325 ma idd2q precharge quiet standby current 428 483 ma idd2n precharge standby current 467 523 ma idd3p active power - down current 317 356 ma idd3n active standby current 491 554 ma idd4r operating burst read current 2202 2645 ma idd4w operating burst write current 2154 2574 ma idd5b burst refresh current 3366 3445 ma idd6 self refresh current: normal temperature range 135 135 ma idd7 operating bank interleave read current 5655 6930 ma t case = 0 c ~ 85 c; v ddq = v dd = 1.35v - 0.0675/ + 0.1v [ 4 g b C 1 r ank, 512 mx 4 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 1283 1378 ma idd1 operating one bank active - read - precharge current 1600 1711 ma idd2p1 precharge power - down current fast exit 285 317 ma idd2q precharge quiet standby current 420 475 ma idd2n precharge standby current 459 515 ma idd3p active power - down current 309 348 ma idd3n active standby current 483 546 ma idd4r operating burst read current 2075 2487 ma idd4w operating burst write current 2123 2534 ma idd5b burst refresh current 3263 3334 ma idd6 self refresh current: normal temperature range 135 135 ma idd7 operating bank interleave read current 5536 6780 ma
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 25 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. t case = 0 c ~ 85 c; v ddq = v dd = 1. 5v 0.075 v [ 8 g b C 2 r ank, 512 mx 4 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 1798 1956 ma idd1 operating one bank active - read - precharge current 2115 2289 ma idd2p1 precharge power - down current fast exit 570 649 ma idd2q precharge quiet standby current 855 966 ma idd2n precharge standby current 935 1045 ma idd3p active power - down current 634 713 ma idd3n active standby current 982 1109 ma idd4r operating burst read current 2693 3200 ma idd4w operating burst write current 2645 3128 ma idd5b burst refresh current 3857 4000 ma idd6 self refresh current: normal temperature range 269 269 ma idd7 operating bank interleave read current 6146 7484 ma t case = 0 c ~ 85 c; v ddq = v dd = 1.35v - 0.0675/ + 0.1v [ 8 g b C 2 r ank, 512 mx 4 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 1766 1925 ma idd1 operating one bank active - read - precharge current 2083 2257 ma idd2p1 precharge power - down current fast exit 570 634 ma idd2q precharge quiet standby current 840 950 ma idd2n precharge standby current 919 1030 ma idd3p active power - down current 618 697 ma idd3n active standby current 966 1093 ma idd4r operating burst read current 2558 3033 ma idd4w operating burst write current 2606 3081 ma idd5b burst refresh current 3746 3881 ma idd6 self refresh current: normal temperature range 269 269 ma idd7 operating bank interleave read current 6019 7326 ma
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 26 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. t case = 0 c ~ 85 c; v ddq = v dd = 1. 5v 0.075 v [ 16 g b C 4 r ank, 1024 mx 4 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 2780 3065 ma idd1 operating one bank active - read - precharge current 3097 3398 ma idd2p1 precharge power - down current fast exit 1140 1299 ma idd2q precharge quiet standby current 1711 1932 ma idd2n precharge standby current 1869 2091 ma idd3p active power - down current 1267 1426 ma idd3n active standby current 1964 2218 ma idd4r operating burst read current 3675 4308 ma idd4w operating burst write current 3627 4237 ma idd5b burst refresh current 4839 5108 ma idd6 self refresh current: normal temperature range 539 539 ma idd7 operating bank interleave read current 7128 8593 ma t case = 0 c ~ 85 c; v ddq = v dd = 1.35v - 0.0675/ + 0.1v [ 16 g b C 4 r ank, 1024 mx 4 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 unit ( - be) ( - cg) idd0 operating one bank active - precharge current 2732 3018 ma idd1 operating one bank active - read - precharge current 3049 3350 ma idd2p1 precharge power - down current fast exit 1140 1267 ma idd2q precharge quiet standby current 1679 1901 ma idd2n precharge standby current 1837 2059 ma idd3p active power - down current 1236 1394 ma idd3n active standby current 1932 2186 ma idd4r operating burst read current 3524 4126 ma idd4w operating burst write current 3572 4174 ma idd5b burst refresh current 4712 4974 ma idd6 self refresh current: normal temperature range 539 539 ma idd7 operating bank interleave read current 6985 8419 ma
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 27 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. standard speed bins ddr3 - 1066 mhz speed bin ddr3 - 1066 unit cl - nrcd - nrp 7 - 7 - 7 ( - be) parameter symbol min max internal read command to first data taa 13.125 20.000 ns act to internal read or write delay time trcd 13.125 - ns pre command period trp 13.125 - ns act to act or ref command period trc 50.625 - ns act to pre command period tras 37.500 9*trefi ns cl=5 cwl=5 tck(avg) 3.000 3.300 ns cwl=6 tck(avg) reserved ns cl=6 cwl=5 tck(avg) 2.500 3.300 ns cwl=6 tck(avg) reserved ns cl=7 cwl=5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cl=8 cwl=5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns supported cl settings 6,7,8 nck supported cwl settings 5,6 nck ddr3 - 1333mhz speed bin ddr3 - 1333 unit cl - nrcd - nrp 9 - 9 - 9 ( - cg) parameter symbol min max internal read command to first data taa 13. 125 (13.125) 5,11 20.000 ns act to internal read or write delay time trcd 13. 125 (13.125) 5,11 - ns pre command period trp 13. 125 (13.125) 5,11 - ns act to act or ref command period trc 49. 125 (49.125) 5,11 - ns act to pre command period tras 36.000 9*trefi ns cl=5 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cl=6 cwl=5 tck(avg) 2.500 3.300 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cl=7 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 * <2.5 * ns cwl=7 tck(avg) reserved reserved ns cl=8 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved reserved ns cl=9 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.500 <1.875 ns cl=10 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.500 * <1.875 * ns supported cl settings 6,7,8,9 nck supported cwl settings 5,6,7 nck
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 28 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing speci fi cations for ddr 3 sdram devices used on module (1066mhz) parameter symbol ddr3 - 1 066 units notes min. max. clock timing minimum clock cycle time (dll off mode) tck (dll_off) 8 - ns average clock period tck(avg) refer to "standard speed bins) ps average high pulse width tch(avg) 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min max.: tck(avg)max + tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - tck(avg) clock period jitter jit(per) - 90 90 ps clock period jitter during dll locking period jit(per, lck) - 80 80 ps cycle to cycle period jitter tjit(cc) 180 180 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 160 160 ps duty cycle jitter tjit(duty) - - ps cumulative error across 2 cycles terr(2per) - 132 132 ps cumulative error across 3 cycles terr(3per) - 157 157 ps cumulative error across 4 cycles terr(4per) - 175 175 ps cumulative error across 5 cycles terr(5per) - 188 188 ps cumulative error across 6 cycles terr(6per) - 200 200 ps cumulative error across 7 cycles terr(7per) - 209 209 ps cumulative error across 8 cycles terr(8per) - 217 217 ps cumulative error across 9 cycles terr(9per) - 224 224 ps cumulative error across 10 cycles terr(10per) - 231 231 ps cumulative error across 11 cycles terr(11per) - 237 237 ps cumulative error across 12 cycles terr(12per) - 242 242 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max ps data timing dqs, dqs# to dq skew, per group, per access tdqsq - 150 ps dq output hold time from dqs, dqs# tqh 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 600 300 ps dq high impedance time from ck, ck# thz(dq) - 300 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 25 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds( base) ac150 75 ps data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 100 ps dq and dm input pulse width for each input tdipw 490 ps data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 tck(avg) dqs, dqs# differential read postamble trpst 0.3 note 11 tck(avg) dqs, dqs# differential output high time tqsh 0.38 - tck(avg) dqs, dqs# differential output low time tqsl 0.38 - tck(avg) dqs, dqs# differential write preamble twpre 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - tck(avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 300 300 tck(avg) dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 600 300 tck(avg) dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 300 tck(avg) dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 tck(avg) dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 tck(avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 tck(avg) dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.2 - tck(avg) dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - tck(avg) command and address timing
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 29 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. dll locking time tdllk 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - ns mode register set command cycle time tmrd 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd pre command period trp act to act or ref command period trc cas# to cas# command delay tccd 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - nck active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd max(4nck, 7.5ns) - active to active command period for 2kb page size trrd trrdmin.: max(4nck, 10ns) trrdmax.: four activate window for 1kb page size tfaw 37.5 - ns four activate window for 2kb page size tfaw 50 - ns command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 125 - ps command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 200 - ps command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 125+150 - ps control and address input pulse width for each input tipw 780 - ps calibration timing power - up and reset calibration time tzqinit 512 - nck normal operation full calibration time tzqoper 256 - nck normal operation short calibration time tzqcs 64 - nck reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 7.5ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck 5.625 ns) tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 tcpdedmin.: - nck power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 tactpdenmax.: - nck timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 nck
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 30 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. tprpdenmax.: - timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry trefpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power down entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max.: - nck asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 ns rtt turn - on taon - 300 300 ps rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 tck(avg) write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - nck dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - nck write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 245 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 245 - ps write leveling output delay twlo 0 9 ns write leveling output error twloe 0 2 ns
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 31 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing speci fi cations for ddr 3 sdram devices used on module (1333mhz) parameter symbol ddr3 - 1333 units notes min. max. clock timing minimum clock cycle time (dll off mode) tck (dll_off) 8 - ns average clock period tck(avg) refer to "standard speed bins) ps average high pulse width tch(avg) 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min max.: tck(avg)max + tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - tck(avg) clock period jitter jit(per) - 80 80 ps clock period jitter during dll locking period jit(per, lck) - 70 70 ps cycle to cycle period jitter tjit(cc) 160 160 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 140 140 ps duty cycle jitter tjit(duty) - - ps cumulative error across 2 cycles terr(2per) - 118 118 ps cumulative error across 3 cycles terr(3per) - 140 140 ps cumulative error across 4 cycles terr(4per) - 155 155 ps cumulative error across 5 cycles terr(5per) - 168 168 ps cumulative error across 6 cycles terr(6per) - 177 177 ps cumulative error across 7 cycles terr(7per) - 186 186 ps cumulative error across 8 cycles terr(8per) - 193 193 ps cumulative error across 9 cycles terr(9per) - 200 200 ps cumulative error across 10 cycles terr(10per) - 205 205 ps cumulative error across 11 cycles terr(11per) - 210 210 ps cumulative error across 12 cycles terr(12per) - 215 215 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max ps data timing dqs, dqs# to dq skew, per group, per access tdqsq - 125 ps dq output hold time from dqs, dqs# tqh 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 500 250 ps dq high impedance time from ck, ck# thz(dq) - 250 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 - ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds( base) ac150 30 ps data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 65 ps dq and dm input pulse width for each input tdipw 400 - ps data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 tck(avg) dqs, dqs# differential read postamble trpst 0.3 note 11 tck(avg) dqs, dqs# differential output high time tqsh 0.4 - tck(avg) dqs, dqs# differential output low time tqsl 0.4 - tck(avg) dqs, dqs# differential write preamble twpre 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - tck(avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 255 255 tck(avg) dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 500 250 tck(avg) dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 250 tck(avg) dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 tck(avg) dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 tck(avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 tck(avg) dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.2 - tck(avg) dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - tck(avg) command and address timing
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 32 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. dll locking time tdllk 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - ns mode register set command cycle time tmrd 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd pre command period trp act to act or ref command period trc cas# to cas# command delay tccd 4 nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - nck active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd trrdmin.: max(4nck, 6ns) trrdmax.: active to active command period for 2kb page size trrd trrdmin.: max(4nck, 7.5ns) trrdmax.: four activate window for 1kb page size tfaw 30 0 ns four activate window for 2kb page size tfaw 45 0 ns command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 65 - ps command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 140 - ps command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 65+125 - ps control and address input pulse width for each input tipw 620 - ps calibration timing power - up and reset calibration time tzqinit 512 - nck normal operation full calibration time tzqoper 256 - nck normal operation short calibration time tzqcs 64 - nck reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 6 ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck ,5.625 ns) tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 tcpdedmin.: - nck power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 tactpdenmax.: - nck
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 33 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 tprpdenmax.: - nck timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry trefpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power down entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max.: - nck asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 ns rtt turn - on taon - 250 250 ps rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 tck(avg) write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - nck dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - nck write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 195 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 195 - ps write leveling output delay twlo 0 9 ns write leveling output error twloe 0 2 ns
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 34 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [ 2 g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] note: device position and scale are only for reference. f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + 0 . 0 4 / - 0 . 0 5 b a c k 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h d e t a i l a 9 . 5 0 1 3 3 . 3 5 + / - 0 . 1 5 u n i t s : m i l l i m e t e r s 3 0 . 0 0 + / - 0 . 1 5 s i d e 4 . 0 0 m a x . 1 . 2 7 + 0 . 0 7 / - 0 . 1 0 1 7 . 3 0 5 . 1 7 5 4 7 . 0 0 d e t a i l b 7 1 . 0 0 5 . 0 0 2 . 5 0 3 . 0 ( x 4 ) s p d / t s r e g i s t e r i n g c l o c k d r i v e r
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 35 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [ 4 g b C 2 r ank s , 256 mx 8 ddr 3 sdrams ] note: device position and scale are only for reference. f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + 0 . 0 4 / - 0 . 0 5 b a c k 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h d e t a i l a 9 . 5 0 1 3 3 . 3 5 + / - 0 . 1 5 u n i t s : m i l l i m e t e r s 3 0 . 0 0 + / - 0 . 1 5 s i d e 4 . 0 0 m a x . 1 . 2 7 + 0 . 0 7 / - 0 . 1 0 1 7 . 3 0 5 . 1 7 5 4 7 . 0 0 d e t a i l b 7 1 . 0 0 5 . 0 0 2 . 5 0 3 . 0 ( x 4 ) s p d / t s r e g i s t e r i n g c l o c k d r i v e r
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 36 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [4g b C 1 r ank, 512 mx 4 ddr 3 sdrams ] note: device position and scale are only for reference. f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b b a c k 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h d e t a i l a 9 . 5 0 1 3 3 . 3 5 + / - 0 . 1 5 u n i t s : m i l l i m e t e r s 3 0 . 0 0 + / - 0 . 1 5 s i d e 4 . 0 0 m a x . 1 . 2 7 + 0 . 0 7 / - 0 . 1 0 1 7 . 3 0 5 . 1 7 5 4 7 . 0 0 d e t a i l b 7 1 . 0 0 5 . 0 0 2 . 5 0 3 . 0 ( x 4 ) s p d / t s r e g i s t e r i n g c l o c k d r i v e r 0 . 8 0 + 0 . 0 4 / - 0 . 0 5
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 37 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [8g b C 2 r ank s , 512 mx 4 ddr 3 sdrams without h/s] note: device position and scale are only for reference. f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + 0 . 0 4 / - 0 . 0 5 r e a r 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h 1 3 3 . 3 5 + / - 0 . 1 5 u n i t s : m i l l i m e t e r s 3 0 . 0 0 + / - 0 . 1 5 2 . 5 0 3 . 0 ( x 4 ) 4 7 . 0 0 5 . 0 0 d e t a i l a d e t a i l b 7 1 . 0 0 9 . 5 0 1 7 . 3 0 5 . 1 7 5 s i d e 4 . 0 0 m a x . 1 . 2 7 + 0 . 0 7 / - 0 . 1 0
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 38 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [ 8 g b C 2 r ank s , 512 mx 4 ddr 3 sdrams with h/s ] note: device position and scale are only for reference. f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + 0 . 0 4 / - 0 . 0 5 r e a r 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h 1 3 3 . 7 5 + / - 0 . 2 5 u n i t s : m i l l i m e t e r s 3 0 . 6 0 + / - 0 . 1 5 s i d e 1 . 2 7 + 0 . 0 7 / - 0 . 1 0 2 . 5 0 m a x 8 . 5 3 . 0 ( x 4 ) 4 7 . 0 0 5 . 0 0 d e t a i l a d e t a i l b 7 1 . 0 0 9 . 5 0 1 7 . 3 0 5 . 1 7 5
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 39 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [ 16 g b C 4 r ank s , 1g x4 (ddp) ddr 3 sdrams ] note: device position and scale are only for reference. f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + 0 . 0 4 / - 0 . 0 5 r e a r 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h 1 3 3 . 7 5 + / - 0 . 2 5 u n i t s : m i l l i m e t e r s 3 0 . 6 0 + / - 0 . 1 5 s i d e 1 . 2 7 + 0 . 0 7 / - 0 . 1 0 2 . 5 0 m a x 8 . 5 3 . 0 ( x 4 ) 4 7 . 0 0 5 . 0 0 d e t a i l a d e t a i l b 7 1 . 0 0 9 . 5 0 1 7 . 3 0 5 . 1 7 5
nt2gc72b89b0nj/nt2gc72b89b 2 nj / nt2gc72c89b0nj / nt2gc72c89b2nj nt4gc72b4pb0nl/nt4gc72 c 4pb0nl / nt4gc72c4pb 2 nl/nt4gc72b8pb0nl/nt4gc72 c 8pb0nl / nt4gc72c8pb 2 nl nt8gc72b4nb 1 nj / nt8gc72b4nb 3 nj/ nt8gc72 c 4nb 1 nj / nt8gc72c4nb 3 nj nt16tc72b4nb1nl/ nt16tc72 c 4nb1nl / nt16tc72c4nb 3 nl 2g b: 256m x 72 / 4gb: 512m x 72 / 8gb: 1 g x 72 / 16gb: 2g x 72 pc3 - 85 00 / pc3 - 10600 registered ddr 3 sdram dimm rev 1.2 40 12 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. revision log rev date modification 0.1 0 2 /20 10 preliminary release 0.5 0 5 /2010 preliminary release 2 1.0 08 /2010 official release 1.1 11/2010 added 1.35v spec . and modify functional block diagram of 1rx4. 1.2 12/2010 added package dimensions of 8gb without heat sink. nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886 - 3 - 328 - 1688 please visit our home page for more information: www.nanya.com printed in taiwan ? 20 10

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